CC1101

PARTNUM: address: 0x30. Chip part number, stores 0x00. Its a label designed to identify the chip and doesn't actually do anything. Typically you combine this with R/W and BURST notation to produce 0xF0 when reading through SPI. 0xF0 = 0x80 | 0x40 | 0x30 0x80 = Read mode 0x40 = Burst 0x30 = PARTNUM for CC1101

VERSION: address: 0x31. Chip version number. It must used in read mode. It stores chip version. `0xF1 = 0x80 | 0x40 | 0x31 0x80 = Read mode 0x40 = Burst 0x30 = PARTNUM for CC1101

NOTE: Look at page 92 of datasheet for more

§Sanity check: Sequence for reading from chip from the side C1101 driver

1. wait 50ms for the module to boot up.
2. wait 1ms more for it to reset its sequence.
3. read PARTNUM from C1101. Tell SPI to trigger a reading sequence using SPI module. This will kickstart a buffering sequence. Once spi tells the driver that buffer is ready, we can read from input.

§Metastability on reading input

In a happy path, all input from SPI like miso, and button presses will align perfectly with clock edges and button will pressed for a single cycle. But that is often not the case.

Metastability is an issue if signal needs to synchronized with the clock domain. Usually its only cases like these:

• external async pins - buttons, switches, signals from other chips
• signals from different

In the case of miso (input), we have data coming in from the module to the FPGA. In this case, data might not be metastable if the connection is weak because sampling voltage is stuck partway between 0 and 1. Metastability decays exponentially fast so the probability that flip is still metastable after time t falls off is very low: e^(-t/τ) where τ is a very small number in picoseconds. We can delay the sampling time by a few cycles to give it more time to stabilize itself into a definitive 1 or 0. That's why for cases where input may be metastable, we want to give it a buffer so that we use the data that was read a few cycles prior.

§Pinouts

Pin	name	direction	Usage
1	GND		ground
2	VCC		1.8v - 3.6v
3	GDD	input	module information (unused)
4	CSN	input	SPI chip select
5	SCK	input	SPI bus clock
6	MOSI	input	Slave in
7	MISO/GD01	output	Slave out
8	GD02	output	Module information output pin